PURPOSE: To enable to connect and run two or more digital differentiation analyzers easily, by connecting the memory to operator of other digital differentiation analyzers.
CONSTITUTION: The digital differentiation analyzers 1, 2 input the output incremebt dz05 of the analyzer 1 to the analyzer 2, ad the memroy A is used for the output increment dz05 of the operator 13 of the analyzer 1, and the output is the increment input of the operator 13 of the analyzer 1. The memory B is added in parallel with the memory A,and the input is the output increment dz05 of the operator 13 of the analyzer 1 the same as the memory A. The analyzers 1, 2 operate while synchronizing to the synchronous signal 10. Accordingly, the memories A, B of the analyzers 1, 2 have the same timing as the control signal 9 performing, and the address input of the memory B is selected, and when the memory read R, the address designation (2), 11 of the analyzer 2 is selected, and when write W, the adress designation number (1), 8 of the analyzer 1 is selected. The inverters 15, 16 perform code conversion for the signal 9 and drive the tristate buffers 17, 18 for signal selection
JIYOU AKIO
KINKO AKIRA
