Title:
割り込み発生回路
Document Type and Number:
Japanese Patent JP4198639
Kind Code:
B2
Abstract:
The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt. If the count value of the main timer 104 is smaller than the value stored in the compare register 105 when the effective edge is detected, the interrupt determination circuit 106 immediately generates an interrupt.
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Inventors:
Takashi Otsuji
Application Number:
JP2004157731A
Publication Date:
December 17, 2008
Filing Date:
May 27, 2004
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G06F9/48; F02D41/26; F02D41/34; G06F9/46; G06G7/70
Domestic Patent References:
| JP2310628A | ||||
| JP4293129A | ||||
| JP2003131890A | ||||
| JP390345U | ||||
| JP2002185469A |
Other References:
前原 貴,保坂 晴哉,プログラム実行時間ばらつき検出機能付エミュレータ装置,東芝技術公開集,株式会社東芝,2000年 3月23日,VOL.18-15,第69頁-第75頁
Attorney, Agent or Firm:
Kiyoshi Inagaki