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Patent Searching and Data


Title:
INTERRUPTING SYSTEM
Document Type and Number:
Japanese Patent JPS6319041
Kind Code:
A
Abstract:

PURPOSE: To perform an interruption processing at high speed, by providing a specific one-byte instruction code when the interruption processing is performed on a control means, and an ordinary processing is stopped, and a processing is jumped to another address.

CONSTITUTION: A microprocessor 1 reads out a code from a memory 2. As a various kinds of instruction codes stored in a memory 2, there are a one-byte instruction which requires no address data, and a two-byte instruction, or a three-byte instruction which requires the address data. The microprocessor 1 judges while byte instruction code is the instruction code, and identifies which code is an instruction code, and which code is a data code, in order. As a result, it is resulted that a jump processing by a conventional three-byte instruction can be realized by the specific one-byte instruction code, and processing speed by the interruption on the processor 1 can be remarkably improved.


Inventors:
KOBAYASHI FUYUKI
Application Number:
JP16440886A
Publication Date:
January 26, 1988
Filing Date:
July 12, 1986
Export Citation:
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Assignee:
SHARP KK
International Classes:
G06F9/48; G06F9/32; G06F9/46; (IPC1-7): G06F9/32; G06F9/46
Attorney, Agent or Firm:
Nishikyo Keiichiro