PURPOSE: To facilitate the interruption multiplexing process without complicating the program structure by setting the interruptions received from each interruption request device under a maskable state idividually at the outside of a processor and under the control of the processor.
CONSTITUTION: It is decided by the state of an FF 4-5 whether the interruption received from an interruption request device 15 having the lowest priority is masked or not among those interruption request devices 13W15. The state of the FF 4-5 is controlled when an order is supplied to an interruption control circuit 4 from a processor 1 via an address bus 11 and a decoder 10. When a masking action is set to the interruption received from the device 15, the due signals are obtained at a mask setting terminal 7 and a chip selection terminal 9 with the order received from the processor 1. These signals reset (mask setting) the FF 4-5 via an AND gate 4-2 and an OR gate 4-3. When the FF 4-5 is released, the due signals are obtained at a mask resetting terminal 8 and the terminal 9 by the order received from the processor 1. Then the FF 4-5 is set via an AND gate 4-1 with a delay.
HIGAKI NORITOSHI
TAKEI TORU
OKUGAWA JUNICHI
