PURPOSE: To execute the priority control of an inputted interruption request signal at a high speed.

CONSTITUTION: Interruption request signal controllers 11-14 and an uninhibitable interruption request signal controller 45, an inputted interruption request signal and an uninhibitable interruption request signal which cannot inhibit reception and the storage contents of an in-execution priority register 16, and an interruption request signal whose priority is the highest or an uninhibitable interruption request signal in the interruption request signals which are compared in order extending from the upperpost level to the lowest level by (n + 1) pieces (n ia a natural number) of timings generated repeatedly by a stage counter 32, and to which 2n priority levels and a designated priority position of every device are detected. In such a way, priority levels of interruption requests are compared at a high speed, and it is possible to cope with the uninhibitable interruption request whose priority is the highest, and also, the case when the same priority is set simultaneously.