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Title:
INTERRUPTION CONTROLLER
Document Type and Number:
Japanese Patent JPS5998256
Kind Code:
A
Abstract:

PURPOSE: To distinguish easily a maskable interruption and a non-maskable interruption from each other, by providing a means which accepts and processes the non-maskable interruption without the influence upon the state of an interruption permission flag for the maskable interruption.

CONSTITUTION: When a non-maskable interruption request signal INT0 is applied, an interruption request flag RQ30 is set. Therefore, a flag EI30 indicating the interruption execution is set, and an OR32 is set to 1 through an FFEX30, and the interruption processing is executed. Since other interruption are inhibited during the execution of the interruption processing, an interruption permission flag EI31 is not changed, and a return instruction RT1 is executed without executing an instruction EI after the execution of the interruption processing, and the control is returned to the original routine. When the instruction RTI is executed, the flag EI30 indicating the execution of the interruption processing for INT0 is reset, and it is determined by the output of the interruption permission flag EI31 whether other interruptions are permitted or not.


Inventors:
KANAYAMA HIDEYO
Application Number:
JP20699382A
Publication Date:
June 06, 1984
Filing Date:
November 26, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F13/24; G06F9/48; (IPC1-7): G06F3/00; G06F9/46
Domestic Patent References:
JPS5295322U1977-07-16
Attorney, Agent or Firm:
Uchihara Shin