Title:
INTERRUPTION PROCESSING SYSTEM FOR INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JP2001084149
Kind Code:
A
Abstract:
To provide an interruption processing system for preventing the generation of any problem in a simple method at the time of accepting interruption just after delay in a pipe line system CPU for processing an instruction having a delay slot.
This interruption processing system, is provided with an instruction decoder 1 for decoding an instruction in a CPU for pipe line-processing a delay instruction having a delay slot and a flag register 2 which can be set according to the instruction. Thus, interruption just after the delay instruction is switched to validity or invalidity according to the state of the flag register 2.
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Inventors:
HARA KAZUHIKO
YAMAURA SHINICHI
KATAYAMA TAKAO
IWANAGA KAZUHIKO
TAKATO KOSUKE
YAMAURA SHINICHI
KATAYAMA TAKAO
IWANAGA KAZUHIKO
TAKATO KOSUKE
Application Number:
JP26016299A
Publication Date:
March 30, 2001
Filing Date:
September 14, 1999
Export Citation:
Assignee:
RICOH KK
International Classes:
G06F9/38; G06F9/46; G06F9/48; (IPC1-7): G06F9/46
Attorney, Agent or Firm:
Torii Hiroshi
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