INTGRATED MOS CIRCUIT

Title:

INTGRATED MOS CIRCUIT

Document Type and Number:

Japanese Patent JPS6184054

Kind Code:

A

Abstract:

1. Monolithic integrated MOS circuit incorporating a memory array (1a, b) composed of electrically programmable memory cells (5), for example EEPROMs, characterized in that the output of at least one memory cell (5) can be connected to a predetermined potential by means of at least one blocking circuit (10a, b) under the control of at least one radiation sensitive sensor (8, 14).

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Inventors:

HARUTOMUUTO SHIYURENKU

Application Number:

JP21089885A

Publication Date:

April 28, 1986

Filing Date:

September 24, 1985

Export Citation:

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Assignee:

SIEMENS AG

International Classes:

G06F21/75; G06F21/86; G06K19/06; G06K19/073; G06F12/14; G07F7/10; G11C5/00; G11C16/02; G11C16/22; G11C17/00; H01L21/8246; H01L21/8247; H01L23/58; H01L27/10; H01L27/112; H01L29/788; H01L29/792; (IPC1-7): G06F12/14; G11C17/00; H01L27/10; H01L29/78

Attorney, Agent or Firm:

Tomimura Kiyoshi

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