Title:
逆元演算装置及びメモリシステム
Document Type and Number:
Japanese Patent JP7414675
Kind Code:
B2
Abstract:
According to one embodiment, in an inverse element arithmetic apparatus, a word unit processing unit, as approximate calculation loop for extended binary GCD process, iterates a first loop in a case where a value of |r−s| is a subtraction threshold or more, and is capable of iterating a second loop instead of the first loop in a case where the value of |r−s| is smaller than the subtraction threshold. In the first loop, values of r, s, a, b, m, and n is updated and an update matrix M is generated or updated. In the second loop, the values of m and n are updated without updating the values of r, s, a, b and the update matrix M. The control unit terminates the loop of the inverse element arithmetic process in a case where a loop number of times of the inverse element arithmetic process reaches a number-of-times threshold.
Inventors:
Hajime Matsui
Application Number:
JP2020153341A
Publication Date:
January 16, 2024
Filing Date:
September 11, 2020
Export Citation:
Assignee:
Kioxia Corporation
International Classes:
G09C1/00; G06F17/10
Domestic Patent References:
| JP11282351A | ||||
| JP2007520728A |
Foreign References:
| US20020095452 |
Other References:
廣吉 慶,拡張2進GCD法+Lehmer法の改良,電子情報通信学会技術研究報告,日本,社団法人電子情報通信学会,2002年03月12日,Vol.101,No.728,pp.139-143
Attorney, Agent or Firm:
Sakai International Patent Office
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