Title:
ISOLATION REGION OF SEMICONDUCTOR AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JPH01120842
Kind Code:
A
Abstract:
PURPOSE: To form an isolation trench between active devices through one time of lithography and, at the same time, to improve the immunity to radiation of the trench by forming sidewall oxide layers on the sidewalls of the trench by using a thermal deposition technique or chemical vapor deposition technique and selectively growing silicon from a semiconductor material containing an exposed silicon area. CONSTITUTION: After a pad oxide layer 10 and a nitride layer 14 are formed on a substrate 12, trench areas 16 in which active devices are to be formed are coated with a photoresist layer, and trenches 18 are left exposed. Then the trenches 18 are filled up by selectively growing silicon or epitaxy 28 in the trenches 19 by using the exposed bottom sections 24 of the trenches as the 'seeds'. Since the growth of the epitaxy 28 is selective, the epitaxy 28 only grows upward from the bottom sections 24 of the trenches and does not grow from the other material than silicon. Then the nitride layer 14 is removed by using an etchant and the first-formed oxide layer 10 is removed. Thus a trench isolation area 32 having a channel stop area 20 surrounding the epitaxy area 28, sidewall oxide layers 26, and a field oxide layer 30 is formed.
Inventors:
KURARENSU UONNSHIN TENGU
Application Number:
JP24219888A
Publication Date:
May 12, 1989
Filing Date:
September 27, 1988
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/76; (IPC1-7): H01L21/76
Domestic Patent References:
| JPS6223128A | 1987-01-31 | |||
| JPS5683046A | 1981-07-07 | |||
| JPS4945195A | 1974-04-30 |
Attorney, Agent or Firm:
Akira Asamura (2 outside)