PURPOSE: To increase a withstanding voltage and a higher limit frequency, when a gate region and source regions that are located on both sides of the gate region are provided in a semiconductor substrate and a J-FET is obtained, by contacting the same conductive type embedded channel region, whose impurity concentration is lower than that of the regions 12 and 13, to the side surfaces of the bottom parts of the regions 12 and 13.
CONSTITUTION: The N type channel region 11 is embedded and formed only in the P type semiconductor substrate 10 but not on the surface layer of the substrate 10 by high energy ion implantation. As for the conditions of the ion implantation, P ions are used, 400keV of acceleration energy is selected, and 3×1014atoms/cm2 of implanting quantity is selected. Then, the N- type source region 12 and drain region 13 are diffused and formed so as to contact with both side surfaces of the region 11. The P+ type gate region 14 is provided at the part in the substrate 10, which is surrounded by the regions 11∼13. In this constitution, the P+-P-N structure of the junction is obtained, the impurity concentration of the substrate 10 can be reduced, and the stray capacity is reduced to a large extent.
OONAKA SEIJI
EZAKI TAKEYA
NAGANO KAZUTOSHI
KAJIWARA KOUSEI
Next Patent: AVALANCHE PHOTODIODE AND MANUFACTURE THEREOF