PURPOSE: To perform roll-over operation through simple circuit constitution, and to reduce the size of an LSI-implemented chip, by judging whether key input processing is performed or not on the basis of the output of a central arithmetic processing circuit.

CONSTITUTION: Various keys A1WA7,WD1WD7 are arranged on plural output signal lines KO1WKO7 of a key input part 1, and various kinds of processing are performed by a CPU4 according to key operation signals from those keys A1WA7,WD1WD7. Data outputted to the data bus DB of this CPU4 are latched by latches F1WF7; the outputs of the latches F1WF4are inputted to NOR circuits 31W34, and those of the latches F5WF7 are inputted to a decoder 9. Further, the outputs of the keys A1WA7,WD1WD7 are supplied to the other-side terminals of the circuits 31W34, whose outputs are supplied to an FF11, the output of which is applied to the CPU4. On the basis of the output of the CPU4, whether key input processing is performed or not is judged to perform roll-over operation through the simple circuit constitution, and LSI-implementation is performed with reduced chip size.