Title:
POWER SYSTEM PROTECTOR
Document Type and Number:
Japanese Patent JP3223302
Kind Code:
B2
Abstract:
PURPOSE: To enable power stop range to be limited only to the system where an accident has occurred by tripping only the breaker of the system where a fault has fault occurred after tripping the bus communication breaker by a logical circuit when a occurs in one bus.
CONSTITUTION: When a grounding fault occurs in the first bus 12, grounding detection signals are output from the detectors 42A, 44A, and 46A of grounding protective relays 42, 44, and 46, and the first and second start signals are output at the same time, respectively, from the AND gates 50 and 56 of a logical circuit 48, and the first timers 52 and the second timer 58 are started. Next, a bus communication breaker 28 is tripped by a trip driver 46B. For this sake, the output of the grounding detection signal from the detector 44A is stopped, and the timer 58 stops. On the other hand, when the start signal is input continuously for a certain time to the timer 52, a timer signal is output, and concurrently when a trip detector 62 detects that the breaker 28 has tripped, a trip signal is output from a gate 54, and the first breaker 14 is tripped.
Inventors:
Suguru Funato
Fumio Wakasa
Yasunobu Fujita
Miho Matsushima
Fumio Wakasa
Yasunobu Fujita
Miho Matsushima
Application Number:
JP33844391A
Publication Date:
October 29, 2001
Filing Date:
December 20, 1991
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H02H7/22; H02H7/26; (IPC1-7): H02H7/22; H02H7/26
Domestic Patent References:
| JP5415147A | ||||
| JP58145040U |
Attorney, Agent or Firm:
Tatsuyuki Unuma