Title:
LAMINATED SEMICONDUCTOR PACKAGE
Document Type and Number:
Japanese Patent JP2939614
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor package allowing the integration capacity in a single semiconductor package to be increased by forming a structure allowing semiconductor chips to be laminated in an LOC-structured package.
SOLUTION: The semiconductor package has leads 1 composed of inner leads 1a having double-stepped parts in the package and bends 1b outside the package and outer leads 1c extending from the bends 1b and houses a lower semiconductor chip 5 having a center pad 4 and upper semiconductor chip 7 having side pads 6. These chips 5, 7 are fixed to the top and bottom faces of the stepped parts of the inner leads 1a through double-sided adhesive insulation members 8, bonded through wires 9 and sealed with a molding body 10, thus laminating the semiconductor chips 5, 7 in the body 10.
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Inventors:
CHO ZAIGEN
Application Number:
JP19225297A
Publication Date:
August 25, 1999
Filing Date:
July 17, 1997
Export Citation:
Assignee:
ERU JII SEMIKON CO LTD
International Classes:
H01L21/60; H01L23/495; H01L23/52; H01L25/065; H01L25/07; H01L23/28; H01L25/18; (IPC1-7): H01L23/52; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP8250537A |
Attorney, Agent or Firm:
Hagiwara Makoto
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