Title:
LAND, MANUFACTURING METHOD, AND MOUNTING METHOD FOR MULTILAYER PRINTED WIRING BOARD
Document Type and Number:
Japanese Patent JP2005044990
Kind Code:
A
Abstract:
To provide a land for mounting a component in a multilayer printed wiring board that has such a structure to effectively prevent the occurrence of a lift-off phenomenon or a land peeling phenomenon, even if a lead-free solder (non-lead solder) with high melting temperature is used for mounting a component.
The land 20 of a multilayer printed wiring board that is formed on the uppermost surface of a multilayer printed wiring board 10 to mount a component is provided with a via hole 21 and a through hole 22 for inserting a component.
More Like This:
| JPH02128451 | IC PACKAGE |
| JPS6326259 | HEATER AND METHOD OF FORMING PREDETERMINED TEMPERATURE CONTOUR |
| JPH04137587 | HYBRID INTEGRATED CIRCUIT DEVICE |
Inventors:
KURASHINA YUICHI
TSURUKAWA KIMIHARU
TSURUKAWA KIMIHARU
Application Number:
JP2003277244A
Publication Date:
February 17, 2005
Filing Date:
July 22, 2003
Export Citation:
Assignee:
SONY CORP
International Classes:
H05K3/34; H05K3/46; (IPC1-7): H05K3/46; H05K3/34
Attorney, Agent or Firm:
Takahisa Yamamoto