Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
LARGE SCALE INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5954255
Kind Code:
A
Abstract:

PURPOSE: To implement an LSI in a short time, by arranging exclusively designed special function blocks at appropriate positions on a cell array substrate, on which basic cells are arranged in an m×n pattern.

CONSTITUTION: A chip 1 has an array structure, wherein basic cells 2 are fundamentally arranged in an m×n pattern. The cells can be arranged so that the number of the cells is freely increased or decreased. Function blocks 3 are arranged depending on the purpose regardless of the restriction imposed by a foundation. Then, the function blocks having a systematic structure such as memories and special purpose blocks such as buffers are arranged at the appropriate positions. The memories are exclusively designed, with the basic structure of the cell array suitable for computer aided design as a fundamental form, and has excellent area efficiency. Then, the special function peculiar to the kind of the device is satisfied without nullifying the features of the cell array substrate, and the LSI can be implemented in a short time.


Inventors:
KAKIMOTO MASAO
Application Number:
JP16448082A
Publication Date:
March 29, 1984
Filing Date:
September 21, 1982
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/02; H01L27/04; (IPC1-7): H01L21/82; H01L27/04
Domestic Patent References:
JPS5342578A1978-04-18
JPS57100747A1982-06-23
Attorney, Agent or Firm:
Uchihara Shin