PURPOSE: To electrically isolate power supply cells, restrain propagation of noise of different kind of power supply cells, make an excessive voltage escape when it is applied to the power supply cell, and prevent electrostatic breakdown.

CONSTITUTION: The width W22 of a real wiring pattern 22 is smaller than the width W23 of a cell frame 23. On the upper layer of the real wiring pattern 22, wiring patterns 24, 25 are formed all over the whole width W23 of the cell frame 23. On the lower layer of the real wiring pattern 22, patterns of a PMOS transistor Tr1 and an NMOS transistor Tr2 are formed. A layout pattern 20 for an I/O cell region on the peripheral part of a semiconductor chip, and layout patterns for an input buffer cell and an output buffer cell are layed out in order so as to be adjacent, thereby constituting a semiconductor device.