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Title:
LAYOUT PATTERN VERIFYING APPARATUS
Document Type and Number:
Japanese Patent JPH05152441
Kind Code:
A
Abstract:

PURPOSE: To obtain a layout pattern verifying apparatus which can efficiently verify a layout of a large scale LSI in a finite operating region of a hard disk.

CONSTITUTION: Operating region size estimating means 8 calculates a necessary operating region size of an operating region 2 for verifying regarding its layer from data amount of each layer for constituting a layout pattern, and examines the operating region size to be used. Verifying item deciding means 11 selects a verifying item to be executed in the size to be used with reference to the necessary size, forms an executing verifying rule, and stores it in executing verifying rule storage means 10. Layout pattern verifying means 4 verifies the layout pattern according to the verifying rule of the means 10. The selection of the verifying item, the verification of the layout pattern are repeated until all the items are completed. Thus, the verification of the pattern can be efficiently executed.


Inventors:
KAMAKURA HIROSHI
Application Number:
JP33965291A
Publication Date:
June 18, 1993
Filing Date:
November 28, 1991
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/82; G06F17/50; (IPC1-7): G06F15/60; H01L21/82
Attorney, Agent or Firm:
Miyazono Junichi



 
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