Title:
LAYOUT PATTERN VERIFYING DEVICE
Document Type and Number:
Japanese Patent JP2708326
Kind Code:
B2
Abstract:
PURPOSE: To obtain the layout pattern verifying device which automatically performs surge breakdown resistance verification.
CONSTITUTION: An input resistance verification module 3, an input resistance contact verification module 4, and an input resistance periphery verification module 5 input an input resistance verification rule 55 and layout information 57 with input/output information respectively, performs the surge breakdown resistance verification for an input resistance itself, an input resistance contact area, and the input resistance and its peripheral area, and outputs its verification result information to a verification result output module 6. Thus, the verification wherein attention is paid to the layout pattern of the input resistance causing surge breakdown is performed to automatically perform the surge breakdown resistance verification.
Inventors:
Hiroshi Ichikawa
Application Number:
JP14390092A
Publication Date:
February 04, 1998
Filing Date:
June 04, 1992
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G06F11/22; G06F17/50; H01L21/66; H01L21/82; G01R31/26; (IPC1-7): G06F17/50; G01R31/26; H01L21/66; H01L21/82
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)