Title:
マルチプレクサセルのレイアウト構造
Document Type and Number:
Japanese Patent JP4531340
Kind Code:
B2
Abstract:
A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.
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Inventors:
Hidaka Itsuo
Application Number:
JP2003050968A
Publication Date:
August 25, 2010
Filing Date:
February 27, 2003
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/82; H01L21/822; H01L27/02; H01L27/04; H01L27/10; H01L27/118; H01L29/73; H03K17/687; H03K17/693
Domestic Patent References:
| JP2003007827A | ||||
| JP5175467A |
Attorney, Agent or Firm:
Ken Ieiri