Title:
LEAK INTEGRATION AVERAGE CIRCUIT AND TRANSMISSION LINE CLOCK REPRODUCING CIRCUIT
Document Type and Number:
Japanese Patent JP3465223
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To simplify a circuit and to reduce circuit scale by constituting the average of an input signal by finding a differential signal, integrating this signal through an integration leakage circuit, finding an integrated value and subtracting it from a phase signal.
SOLUTION: In a differential circuit 1, a register 11 outputs an input phase signal X while delaying it just for one clock cycle and a subtracter 12 inputs the input phase signal X and delay signal and inputs a difference E between both the signals to the integration leakage circuit 2. In the integration leak circuit 2, an adder 13 adds the leakage integrated value supplied from a register subtracter 14 and the differential signal E supplied from the differential circuit 1, finds an integrated value Y and supplies it to a subtracter 17. The register subtracter 14 subtracts the delayed integrated value supplied from a register 16 and a leakage value supplied from a leakage coefficient circuit 15 and outputs an integrated value from which the leakage value is subtracted. The subtracter 17 subtracts the integrated value Y from the input signal X and a fluctuation (namely inclination) averaged phase signal Z is outputted.
Inventors:
Norio Suzuki
Application Number:
JP28603698A
Publication Date:
November 10, 2003
Filing Date:
September 22, 1998
Export Citation:
Assignee:
NEC Engineering Co., Ltd.
International Classes:
G06F7/00; H04L7/033; H04L25/40; (IPC1-7): G06F7/00; H04L7/033; H04L25/40
Domestic Patent References:
| JP10229423A | ||||
| JP548562A | ||||
| JP9505705A |
Attorney, Agent or Firm:
Masahiro Fukuyama