Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
LEARNING CIRCUIT FOR NEURAL NETWORK
Document Type and Number:
Japanese Patent JPH0424865
Kind Code:
A
Abstract:

PURPOSE: To accelerate learning of a neural network and to simplify the hardware structure by applying an accumulation signal and a high frequency signal component to a neural network after mixing them together and controlling the parameter of the neural network.

CONSTITUTION: A neural network 7 is provided together with an input pattern generator 8, an error detector 9, a parameter control part 10, and a teacher pattern generator 11. In a learning state of the network 7, the output signal of the network 7 is compared with a teacher signal and an error signal 104 is produced. Then the correlation is obtained between the signal 104 and the component of a prescribed high frequency signal 102. The correlation detecting signals 103 are sequentially accumulated in terms of time. At the same time, the accumulation signal 100 is mixed with a high frequency signal component 101 and applied to the network 7. Thus the parameter of the network 7 is controlled. As a result, the network 7 is learnt at a high speed and the hardware structure is simplified.


Inventors:
MATSUMOTO TAKAO
Application Number:
JP12928090A
Publication Date:
January 28, 1992
Filing Date:
May 21, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06G7/60; G06F15/18; G06N3/08; G06N99/00; (IPC1-7): G06F15/18; G06G7/60
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)



 
Next Patent: JPH0424866