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Title:
LIMIT CYCLE REDUCTION SYSTEM OF DIGITAL FILTER
Document Type and Number:
Japanese Patent JPS5571315
Kind Code:
A
Abstract:

PURPOSE: To reduce the limit cycle generated when input signals are not inputted to a digital filter, by providing a limit cycle reducing circuit.

CONSTITUTION: Analogue signals inputted to input terminal 1 are converted to digital signals by A/D converter 2. Next, these digital signals are inputted to D/A converter circuit 4 after the digital operation of a finite word length in digital filter 3, and signals where a prescribed frequency characteristic is given are obtained at output terminal 5. In limit cycle reducing circuit 6, presence or absence of input analogue signals is detected; and if input analogue signals are absent for a fixed time, output signals of integrator 7 which passed switch 8 are supplied to adder 10 and are added to the reference voltage from reference voltage generation source 11 to change the zero level reference voltage of A/D converter 2. Thus, output signals of output terminal 5 converge to 0, and the limit cycle is eliminated.


Inventors:
KASUGA MASAO
SATOU MASAAKI
MATSUSHIGE TAKASHI
Application Number:
JP14412078A
Publication Date:
May 29, 1980
Filing Date:
November 24, 1978
Export Citation:
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Assignee:
VICTOR COMPANY OF JAPAN
International Classes:
H03H17/04; (IPC1-7): H03H17/02



 
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