Title:
LOGARITHMIC CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JP3333239
Kind Code:
B2
Abstract:
PURPOSE: To provide the logarithmic conversion circuit enlarging the operational range of low energy consumption by supplying current from both of 1st and 2nd transistors Tr and 3rd and 4th Tr to an impedance element and performing logarithmic conversion with the 3rd and 4th Tr.
CONSTITUTION: The collector current of 1st and 2nd Tr Q1 and Q2 is turned to a current value β-fold (β is an amplification factor) as large as a base current IB when it is observed from the base current IB of the Tr Q1 and Q2. This current is fed back to the bases of Tr Q3 and Q4 and further amplified β-fold, and the input current IB is amplified to β*β-fold. Namely, the current flow from both of the Tr Q1 and Q2 and the Tr Q3 and Q4 to an impedance element RE, and the logarithmic conversion is performed by the Tr Q3 and Q4. With the current amplifying functions of these Tr Q3 and Q4, the transconductance of the entire circuit can be enlarged. Thus, the logarithmic conversion is enabled over the wide voltage amplitude range of an input signal Vin without increasing an operating current, namely, without increasing current consumption.
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Inventors:
Mikio Koyama
Tadashi Arai
Tadashi Arai
Application Number:
JP20548692A
Publication Date:
October 15, 2002
Filing Date:
July 31, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03G11/08; G06G7/24; (IPC1-7): H03G11/08
Domestic Patent References:
| JP63142910A | ||||
| JP6196810A | ||||
| JP6254242B1 |
Attorney, Agent or Firm:
Takehiko Suzue