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Patent Searching and Data


Title:
LOGIC ANALYZER
Document Type and Number:
Japanese Patent JPS6057261
Kind Code:
A
Abstract:

PURPOSE: To measure an efficiency of a program by counting time between prescribed digital signals, and the number of times of generation of signals.

CONSTITUTION: A printer 1300, a self-test probe driving module 1200 and a keyboard 1100 are connected to a microprocessor module 800. Also, a display driving module 900, a display control module 700 and an acquisition system part 250 are connected through a communication bus 600 to the module 800. The acquisition system part 250 is constituted of a measurement control module 40, an index module 300, and a state recognition module 200, and a data probe 100 is connected to the module 200. Plural digital signals are inputted from the probe 100, and a prescribed signal in the input signal is stored in the acquisition system part 250. In this state, a time interval between prescribed signals or the number of times of generation of a digital signal between the prescribed signals is measured by the module 800.


Inventors:
JIYOOJI EE HAAGU
OODAGURASU FUOTSUGU
GOOTON EE GURIINREI
SUTEIIBU EE SHIEPAADO
EFU DANKAN TERII
Application Number:
JP4897684A
Publication Date:
April 03, 1985
Filing Date:
March 14, 1984
Export Citation:
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Assignee:
HEWLETT PACKARD YOKOGAWA
International Classes:
G01R13/28; G01R31/28; G06F11/22; G06F11/25; G06F17/40; (IPC1-7): G01R13/20
Attorney, Agent or Firm:
Hasegawa Tsugio