Title:
LOGIC CIRCUIT DESIGN INFORMATION DISPLAY DEVICE
Document Type and Number:
Japanese Patent JPH01184579
Kind Code:
A
Abstract:
PURPOSE:To efficiently perform the generation of a test pattern by arranging and displaying the relation of a circuit whose function is described written in a hardware descriptive language in the case of generating the test pattern to operate the circuit whose function is described at a function designing stage. CONSTITUTION:Functional description 101 whose function is designed by using the hardware descriptive language is interpreted by a net conversion routine 102, and is converted to net data 103. Next, by tracing the net data 103 by a bus extraction routine 104 and analyzing connection relation, a bus on which a data signal is propagated is extracted, then, a bus list 105 is generated. And based on the condition tracing routine 106 of the bus, the condition of data propagation is traced, respectively. By designating a value output to be taken by the condition at the time of tracing the condition of the bus, an activated test pattern 107 to satisfy respective condition can be obtained. The connection relation of the net data 103 and the relation of the condition, etc., are displayed in a form easy to be recognized.
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Inventors:
TAKEI TSUTOMU
Application Number:
JP826588A
Publication Date:
July 24, 1989
Filing Date:
January 20, 1988
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Noriyuki Noriyuki (1 person outside)