PURPOSE: To provide the logic circuit making high speed logic operation.
CONSTITUTION: A MOS transistor(TR) pair 2 in which MOS TRs TP1,TN1 of different types are connected in series and a MOS TR pair 3 in which a MOS TRs TN 2 and TP2 are connected in series are connected between a high level potential supply Vcc and an output terminal OUT. Furthermore, MOS TR pairs 4,5 in which MOS TRs TN3,TN4 and TP3,TP4 of the same types are connected in series are connected between the output terminal OUT and a low level potential supply Vss. The PM0S TRs TP1-TP4 and NMOS TRs TN1-TN4 being components of the MOS TR pairs 2-5 are immediately switched on or off based on input signals A,B received by each gate. Then an output signal X is provided based on the MOS TR pairs 2-5 whose MOS TRs connected in series are both switched on.
YAMAMOTO TAKAHIRO
YAMAGUCHI SHUHEI
UKAI HIROAKI
FUJITSU VLSI LTD