Title:
LOGIC COMPOSING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2863453
Kind Code:
B2
Abstract:
PURPOSE: To easily generate a semiconductor integrated circuit which is low in power consumption without causing an increase in the delay time of a critical path by performing logic composition so that the whole combinational circuit having the critical path is driven by a high-voltage source.
CONSTITUTION: The semiconductor integrated circuit consists of many registers 2, 4, 6, and 8 and many combinational circuits 1, 3, 5, and 7 positioned between those registers, and some combinational circuits have critical paths. A level converting circuit is arranged at the register position in front of the combinational circuit having the critical path and the combination circuit which has the logical path is driven by the high-voltage source. Other combinational circuits which have no critical path are driven by a low-voltage source. Thus, the combinational circuit having the critical path is driven by the high-voltage source, so the time delay of the critical path can be suppressed below a delay upper limit value which is allowed as to the design. The number of required converting circuits is decreased to a small number and the design is made extremely easy.
Inventors:
OBARA KAZUTAKA
Application Number:
JP615495A
Publication Date:
March 03, 1999
Filing Date:
January 19, 1995
Export Citation:
Assignee:
MATSUSHITA DENKI SANGYO KK
International Classes:
H01L21/82; G06F17/50; H03K19/0185; (IPC1-7): G06F17/50; H01L21/82; H03K19/0185
Domestic Patent References:
| JP5574390A | ||||
| JP5102306A | ||||
| JP5299624A |
Other References:
【文献】米国特許5612892(US,A)
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)
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