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Title:
LOGICAL GATE CIRCUIT
Document Type and Number:
Japanese Patent JPS5482158
Kind Code:
A
Abstract:

PURPOSE: To secure the limitation of the overcurrent of the buffer transistor, which can be applied effectively to the tri-state circuit or the like, by providing the overcurrent detecting transistor and the current limiting transistor.

CONSTITUTION: The npn-type overcurrent detecting TrT15 and npn-type current limiting TrT16 are provided to the TTL logic gate circuit with buffer formed with the conventional npn-type transistor Tr. When the current of over a fixed level flows to buffer TrT12 with the overlap voltage of over 0.7V set to resistance R12, T15 is turned on. Thus, the base current flows to T16 to turn it on, the base current of T12 is absorbed into T16, and the collector-emitter voltage is limited for TrT12. Also, the current value to turn T15 on can be altered by connecting the emitter of T15 to the intermediate tap of R12.


Inventors:
UNO SHIYUUICHI
OOTA MICHIHIKO
Application Number:
JP15015277A
Publication Date:
June 30, 1979
Filing Date:
December 14, 1977
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K19/0175; H03K19/003; H03K19/088; (IPC1-7): H03K19/08



 
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