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Patent Searching and Data


Title:
LOGICAL SIMULATION METHOD
Document Type and Number:
Japanese Patent JPH03191476
Kind Code:
A
Abstract:

PURPOSE: To accurately detect the formation time of an oscillating condition of a latch by providing the logical simulation system with a means for recognizing and extracting the latch based upon the connecting information of logical circuits and detecting the formation of the oscillating condition of the latch and its time.

CONSTITUTION: Logical connection information is compiled to form an intermediate type file. Then a circuit for recognizing the latch from the formed file and detecting the oscillation of the latch and its time is added to form an intermediate type file. The link processing of the intermediate type file is executed together with a library. Then, hierarchical development or the like of the logical connection information is executed, a file expressed by the reference element of simulation is simulated together with a test vector impressed to the circuit and the simulated result is edited to form a file.


Inventors:
KATOU HATSUNORI
Application Number:
JP33205489A
Publication Date:
August 21, 1991
Filing Date:
December 20, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Shin Uchihara