Title:
LOGICAL SUM CIRCUIT
Document Type and Number:
Japanese Patent JPS5331927
Kind Code:
A
Abstract:
PURPOSE: To obtain a new full adder circuit which can obtain a high response velocity using MIS transistors in a considerably small number compared with teh conventional case.
Inventors:
KASAI RIYOUTA
KIMURA TADAKATSU
KIMURA TADAKATSU
Application Number:
JP10650876A
Publication Date:
March 25, 1978
Filing Date:
September 06, 1976
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F7/501; G06F7/50; (IPC1-7): G06F7/50
Foreign References:
| US3767906A | 1973-10-23 |