Title:
LOW CAPACITY FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS5878466
Kind Code:
A
Abstract:
A compact field effect transistor having extremely low source/drain to substrate capacitance is disclosed, together with a method of fabricating it. The source 27 and drain 25 regions of the FET are fabricated on an underlying layer of insulating material 12, typically silicon dioxide, while the gate region including a channel 24, is fabricated directly on the semiconductor substrate 10. The source/drain 27/25 and gate 24 regions are all simultaneously formed by deposition of a single layer of epitaxial silicon 21. In this manner a monocrystalline silicon gate region 24 is created with polycrystalline silicon source/drain regions 27/25. The different rate of growth of silicon dioxide over monocrystalline 24 and polycrystalline silicon 27/25 is utilized to create the gate oxide, while an overlying layer of doped polycrystalline silicon 30 serves as the gate electrode. The source/drain regions are typically doped by an impurity diffused from a layer of phosphorous glass deposited between the insulating material and the source/drain regions.
Inventors:
MAJIYUKAARU BII BORA
Application Number:
JP18223382A
Publication Date:
May 12, 1983
Filing Date:
October 19, 1982
Export Citation:
Assignee:
FAIRCHILD CAMERA INSTR CO
International Classes:
H01L29/78; H01L21/20; H01L21/316; H01L21/336; H01L29/04; H01L29/06; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Kazuo Kobashi