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Title:
LOW-ORDER DEVELOPMENT AUTOMATING SYSTEM
Document Type and Number:
Japanese Patent JPH03260872
Kind Code:
A
Abstract:

PURPOSE: To select optimum configuration by describing the designation of functions and the designation of configuration for a logic unit and preparing one of a logic circuit with wiring logic and a logic circuit with a microprogram or a logic circuit mixing those both configuration systems according to the designation of the same function by using those descriptions.

CONSTITUTION: Based on the designation of the functions for the logic unit storing a file, the logic circuit at a logic gate level is prepared by a logic synthesizing program 39, and the microprogram at a bit pattern level is prepared by a microprogram compiler 38. When preparing the logic circuit at a low-order level from function specification by using a switch to change over the logic synthesizing program 39 and the micorprogram compiler 38 based on the designation of the logic configuration, the logic circuit and the microprogram are prepared while being selected according to the designation of one function. Thus, the optimum logic configuration can be selected.


Inventors:
KOBAYASHI KAZUO
WAKABAYASHI HARUO
OKADA KATSUYUKI
WAKIMURA YOSHIAKI
Application Number:
JP6074090A
Publication Date:
November 20, 1991
Filing Date:
March 12, 1990
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Masatoshi Isomura



 
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