Title:
LSI TESTER
Document Type and Number:
Japanese Patent JP2002350507
Kind Code:
A
Abstract:
To alleviate an operator's load for a calibrating work of an LSI tester.
A performance board 14 is an interface board for connecting a device 16 to be tested to various type testing units of this LIS tester, and further can be connected by a calibrating circuit. The device 16 and the calibrating circuit are switched by a relay, and any of the device 16 and the calibrating circuit is connected to each testing unit of the tester. A calibration managing unit 46 contains a circuit necessary to calibrate to self-diagnose, and manages a counting time or calibrating data of the time. The unit 46 switches the device 16 and the calibrating circuit on the board 14, and executes calibrating of all the testing units.
Inventors:
CHIKA HIDEYUKI
YANAGIHARA NOBUYUKI
MUKAI SHINPEI
YOSHIMURA TAKEHIRO
YANAGIHARA NOBUYUKI
MUKAI SHINPEI
YOSHIMURA TAKEHIRO
Application Number:
JP2001160413A
Publication Date:
December 04, 2002
Filing Date:
May 29, 2001
Export Citation:
Assignee:
RICOH KK
International Classes:
G01R31/28; G01R35/00; G01R31/26; (IPC1-7): G01R31/28; G01R31/26; G01R35/00
Attorney, Agent or Firm:
Noguchi Shigeo
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