Title:
MRAMの伝導線上の磁束集中被覆材料
Document Type and Number:
Japanese Patent JP2005519482
Kind Code:
A
Abstract:
A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
Inventors:
Moller, Janal A.
Darthau, John
Kyler, Kelly
Engel, Bradley N.
Glinke Witch, Gregory W.
Riso, Nicholas Di.
Darthau, John
Kyler, Kelly
Engel, Bradley N.
Glinke Witch, Gregory W.
Riso, Nicholas Di.
Application Number:
JP2003575387A
Publication Date:
June 30, 2005
Filing Date:
February 27, 2003
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L27/105; C25D5/12; G11C11/15; G11C11/16; H01L21/00; H01L21/4763; H01L21/8246; H01L27/22; (IPC1-7): H01L27/105
Attorney, Agent or Firm:
Mamoru Kuwagaki