Title:
MANUFACTURE OF CMOS ELEMENT FOR IMPROVING MOBILITY OF ELECTRON AND HOLE
Document Type and Number:
Japanese Patent JP3852068
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To simultaneously improve mobility of electrons in an NMOS element and mobility of holes in a PMOS element by forming a semiconductor layer portion to be formed so that the PMOS element receives a compression stress and the NMOS element receives a small stress.
SOLUTION: A semiconductor layer 13 portion limited by a first field oxide film 23 receives a compression stress at the time of a thermally oxidizing step for forming the film 23. When the field oxide film is formed in the oxidizing step, the semiconductor layer receives the compression stress. When the field oxide film is formed in a trench step, the stress applied to the semiconductor layer is reduced. Accordingly, since a PMOS element is formed in the layer 13 portion in which the stress exists, mobility of hole in the PMOS element is increased, and mobility of electrons in an NMOS element is increased in the layer 13 portion limited by a second field oxide film 27 of a trench type since the stress existing therein is small.
Inventors:
Lee Jong
Cao Kei Tin
Cao Kei Tin
Application Number:
JP18189099A
Publication Date:
November 29, 2006
Filing Date:
June 28, 1999
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/762; H01L21/20; H01L27/092; H01L21/76; H01L21/8238; H01L21/84; H01L27/08; H01L27/12; H01L29/786; (IPC1-7): H01L29/786; H01L21/762; H01L27/08; H01L27/12
Domestic Patent References:
| JP10093101A | ||||
| JP7058194A | ||||
| JP11054756A | ||||
| JP10092947A | ||||
| JP9219524A | ||||
| JP8242002A |
Other References:
Hole Mobility Improvement in Silicon-on-Insulator and Bulk Silicon Transistors Using Local Strain,1997 International Electron Devices Meeting technical digest,1997年,P.939-941
LOCOS-Induced Stress Effects on Thin-Film SOI Devices,IEEE Transactions on Electron Devices,1997年,Vol.44, No.4,P.646-650
Stress Minimization in Deep Sub-Micron Full CMOS Devices by Using an Optimized Combination of the Trench Filling CVD Oxides,1997 International Electron Devices Meeting technical digest,1997年,P.669-672
LOCOS-Induced Stress Effects on Thin-Film SOI Devices,IEEE Transactions on Electron Devices,1997年,Vol.44, No.4,P.646-650
Stress Minimization in Deep Sub-Micron Full CMOS Devices by Using an Optimized Combination of the Trench Filling CVD Oxides,1997 International Electron Devices Meeting technical digest,1997年,P.669-672
Attorney, Agent or Firm:
Kyosei International Patent Office