Title:
MANUFACTURE OF DMOS FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JP3416214
Kind Code:
B2
Abstract:
PURPOSE: To reduce the possibility that a matching error is generated, and to prevent polycrystalline silicon stringer by reducing the masking process of a transistor manufacturing process.
CONSTITUTION: The masking process steps of a transistor manufacturing process is reduced to six in number. Therefore, a P+-region is doped, a silicone layer 102 is formed at an opening for growing an LOCOS 118, a part of a photoresist is formed, and trenches 120, 122, 124, and 126 are formed. Next, one part of a polycrystalline silicon layer 132 is formed by using one part of the photoresist, one part of a BPSG layer 126 is removed, and a terminal region with the P+- region and a terminal region with the polycrystalline silicone in the trench 124 are formed. Then, one part of a metallic layer 160 is removed, a metallic source electrode 160a and a metallic gate finger 160b are formed, one part of a surface-processing layer 162 is removed, and the parts of a gate-bonding pad and a source-bonding pad are exposed. Thus, an N-channel vertical DMOS transistor is obtained.
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Inventors:
Size-Hong Kwang
Huang Xie
Mike F Chang
Yes-Shi Ho
King O'Young
Huang Xie
Mike F Chang
Yes-Shi Ho
King O'Young
Application Number:
JP21515493A
Publication Date:
June 16, 2003
Filing Date:
August 06, 1993
Export Citation:
Assignee:
SILICONIX INCORPORATED
International Classes:
H01L21/265; H01L21/316; H01L21/318; H01L21/336; H01L21/76; H01L29/06; H01L29/78; (IPC1-7): H01L21/336; H01L21/316; H01L21/76; H01L29/78
Domestic Patent References:
| JP1146367A | ||||
| JP60100469A | ||||
| JP5326544A |
Attorney, Agent or Firm:
Youichi Ohshima