PURPOSE: To eliminate an increase in a length of a channel even if a region for reducing a resistance component is formed by employing a diffusion source layer having an interval to a gate electrode in the case of forming a first conductivity type third region formed on a surface of a second region.

CONSTITUTION: A polycrystalline silicon layer is deposited on a surface of a second region of an n- type layer through an insulating film 6, and patterned to form a gate electrode 7. Then, a thin film 14 containing boron in a high concentration is formed, and a pattern of a resist layer 15 is formed thereon. With the layer 15 as a mask the electrode 7, the films 8, 14 are etched, and the layer 15 is then removed. Here, the film 14 remaining on the surface of an n-type layer 22 becomes a diffusion source layer 16. Then, boron is diffused from the layer 16 in the layer 22 by heat treating to form a third region of a p+ type layer 3. Thus, in order to prevent a latchup, even if formation of the third region by diffusing is deeply conducted, the length of channel is not increased.