Title:
MANUFACTURE OF INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH05175237
Kind Code:
A
Abstract:
PURPOSE: To fabricate a field effect transistor having reduced size in the vertical direction while decreasing the number of fabrication steps by forming an interconnection region, a source region and a drain region, opening a channel region and then depositing a layer for forming a channel. CONSTITUTION: In an inverted arrangement, a gate 2 is formed along with a gate oxide 12 and then a thick polycrystalline region 24 is deposited to form contacts with source and drain as well as the source and drain themselves. That region is then doped and patterned to form an opening for channel. Subsequently, a second thin polycrystalline region 23 is deposited and patterned. The polycrystalline region 23 provides a thin channel required for the transistor to achieve a low current in off state while the thick polycrystalline region 24 provides a low resistance interconnection and low resistance to source and drain. According to the method, size is reduced in the vertical direction while simplifying the filling step.
Inventors:
NADEIA RIFUSHITSU
RONARUDO JIYOSEFU SHIYUTSUTSU
RONARUDO JIYOSEFU SHIYUTSUTSU
Application Number:
JP16184892A
Publication Date:
July 13, 1993
Filing Date:
May 29, 1992
Export Citation:
Assignee:
AMERICAN TELEPHONE & TELEGRAPH
International Classes:
H01L27/12; H01L21/3213; H01L21/336; H01L21/822; H01L29/78; H01L29/786; (IPC1-7): H01L21/336; H01L27/12; H01L29/784
Domestic Patent References:
| JPS5893372A | 1983-06-03 | |||
| JPS63107068A | 1988-05-12 | |||
| JPH0250483A | 1990-02-20 | |||
| JPH0216777A | 1990-01-19 | |||
| JPS62213165A | 1987-09-19 |
Attorney, Agent or Firm:
Hirofumi Mimata