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Title:
MANUFACTURE OF LAMINATED WAFER
Document Type and Number:
Japanese Patent JPH05226305
Kind Code:
A
Abstract:

PURPOSE: To obtain a robust laminated semiconductor wafer wherein cracks are not generated on the surface when mirror surface polishing process is performed by applying large load.

CONSTITUTION: The surface of a semiconductor wafer 110 on the side where a semiconductor element is formed, out of two laminated semiconductor wafers 110, 120, is polished to obtain a specified thickness. From the polished semiconductor wafer 110 toward the other semiconductor wafer 120, sloping down taper type beveling is performed on the whole of outer peripheral part 101 of the laminated semiconductor wafer 100, thereby obtaining a lamination semiconductor wafer wherein a taper part is formed on the outer peripheral part. After that, the surface of a semiconductor wafer 110 on the side where a semiconductor element is to be formed is subjected to mirror polishing. The radius of the semiconductor wafer wherein the taper part is formed does not become small, and the shape is hard to generate cracks. Thereby cracks or the like are not generated when mirror surface polishing or the like is performed.


Inventors:
NAITO SHINJI
AOSHIMA TAKAAKI
Application Number:
JP5756792A
Publication Date:
September 03, 1993
Filing Date:
February 10, 1992
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/02; H01L21/304; H01L27/12; (IPC1-7): H01L21/02; H01L21/304
Attorney, Agent or Firm:
Tomio Ohinata