Title:
MANUFACTURE OF MEMORY CELL TRANSISTOR
Document Type and Number:
Japanese Patent JPH1187542
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To enable microminiaturization of a memory cell transistor. SOLUTION: Taper-etching is applied to a polycrystalline silicon layer 22 formed on a silicon substrate 20 to form recesses 24. After a silicon oxide layer 25 and an SOG(spin-on-glass) layer are formed for filling the recesses 24 and the surface has been planarized, the silicon oxide layer and the SOG layer except the parts in the recesses 24 are removed by etching-back. The polycrystalline silicon layer 22 is selectively removed so as to correspond to the recesses 24 and floating gates 29 which have acute protrusions are formed on the corner parts.
Inventors:
NISHIGUCHI AKIRA
Application Number:
JP24305297A
Publication Date:
March 30, 1999
Filing Date:
September 08, 1997
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L29/788; H01L29/792; H01L27/115
Attorney, Agent or Firm:
Koji Yasutomi (1 person outside)
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