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Patent Searching and Data


Title:
MANUFACTURE OF MIS TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0258267
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption of a mask ROM, prevent latchup, and improve the reliability of an integrated circuit by forming an MISFET having a second threshold value by implanting oxygen in the source region, the drain region, etc., of the MISFET having a first threshold voltage.

CONSTITUTION: When a semiconductor integrated circuit provided with a non- volatile storage function composed of an MISFET is manufactured, an MISFET having a first threshold voltage and an MISFET having a second threshold voltage are arranged. The first MISFET is constitued of the following; a source.drain region 105 of high impurity concentration, and a semiconductor region 103 which is formed between the source.drain region 105 and a channel forming region and has the same conductivity type as the source.drain region 105 and a concentration lower than the region 105. The second MISFET is formed by implanting oxygen in the source region, the drain region or the low concentration semiconductor region 103 of the above MISFET. For example, the semiconductor region 103 is turned into a state 107 where silicon and silicon oxide are mixed, by performing annealing after oxygen 106 is introduced in the semiconductor region 103 in order to write data.


Inventors:
TANAKA KAZUO
Application Number:
JP20903788A
Publication Date:
February 27, 1990
Filing Date:
August 23, 1988
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L29/78; H01L21/8246; H01L27/112; (IPC1-7): H01L27/112; H01L29/784
Attorney, Agent or Firm:
Masanori Ueyanagi (1 outside)