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Title:
MANUFACTURE OF MULTILAYER PRINTED CIRCUIT SUBSTRATE
Document Type and Number:
Japanese Patent JPH01209794
Kind Code:
A
Abstract:

PURPOSE: To eliminate adverse influence of dimensional change of an inner layer plate in a step of forming a circuit and to form a multilayer plate having high density by forming a guide hole for a laminated layer after a circuit pattern is formed.

CONSTITUTION: After a photomask is aligned with a registration hole 2 for the photomask formed on an inner layer plate 1 as a reference, a circuit pattern 4 is formed by a photoetching method. In this case, reference patterns 5 are formed simultaneously with the pattern 4 at the four corners of the plate 1, and a pattern corresponding to the mark 4 is added on the photomask to form a picture. Then, with the working origin 3 of the plate 1 as a reference the coordinates of the position of the previous reference mark 5 are measured. A displacement from the coordinates 5 of the designed position of the mark 5 is calculated, and a working origin correcting amount is obtained. Then, the value of the correcting amount is added to opening information of the plate 1, and a guide hole 7 for a laminated layer is formed by an N/C perforator. The plate 1 formed with the hole 7 and a prepreg 10 are alternately disposed on a jig 9 for the laminated layer on which a positioning pin 8 is planted, and thermally press-bonded to obtain a multilayer plate.


Inventors:
ASANO TOMOAKI
KUWATA HISASHI
Application Number:
JP3591288A
Publication Date:
August 23, 1989
Filing Date:
February 17, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Domestic Patent References:
JPS62131595A1987-06-13
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)