Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE HAVING INSULATED ISOLATION LAYER
Document Type and Number:
Japanese Patent JPS589334
Kind Code:
A
Abstract:
PURPOSE:To reduce parasitic capacitance by producing an anodic oxidation layer to a depth of 2-30mum from the one main surface of a Si substrate, bonding a supporting substrate to this substrate and forming elements in the region isolated by an insulation layer extending from the surface to the anodic oxidation layer. CONSTITUTION:An N<+> layer 2 with an approximate thickness of 20mum is formed to an N type si substrate 1, and to this N<+> layer 2 an anodic oxidation layer 3 with 2-30mum of thickness is formed. A supporting Si substrate 4 is bonded to the substrate using a dielectric adhesive agent 5. An N layer 1 of the substrate 1 is etched to an approximate thickness of 20mum, elements 7a-7c are formed and electrodes are made by providing an opening to each region of SiO211. Then dielectric isolation regions 12 extending to the anodic oxidation layer 3 are provided at the boundaries of each element. Due to the use of the anodic oxidation layer 3 having a 2-30mum thickness parasitic capacitance can be extremely reduced as compared with the P-N junction isolation. The elimination of the epitaxial growth process provides easy of manufacturing. Also, the making of the N<+> layer before anodic oxidation and bonding of the substrate 4 permits easy formation and controlling.
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Inventors:
OGINO MASAHIRO
Application Number:
JP10643081A
Publication Date:
January 19, 1983
Filing Date:
July 08, 1981
Export Citation:
Assignee:
SANKEN ELECTRIC CO LTD
International Classes:
H01L21/76; H01L21/316; H01L21/331; H01L21/762; H01L29/73; (IPC1-7): H01L21/94; H01L29/72
Domestic Patent References:
| JPS4821784A | ||||
| JP45016741A | ||||
| JPS5246798A | 1977-04-13 |
Attorney, Agent or Firm:
Takano Noritsuji
Next Patent: JPS589335