Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH05267663
Kind Code:
A
Abstract:
PURPOSE: To form a front gate electrode without positional deviation from a back gate electrode, regarding the manufacturing method of a double gate structure MOS transistor provided with a front gate electrode and a back gate electrode.
CONSTITUTION: The uneven shape of a conducting layer for alignment in an alignment mark region P which is formed at the same time as a back gate electrode 14 is set as the reference, and a polycrystalline silicon layer 24 is patterned, thereby forming a front gate electrode 28 aligned with the back gate electrode 14, on a gate oxide film 23 in an element region Q.
Inventors:
Koji Kimoto
Takao Miura
Takao Miura
Application Number:
JP5992592A
Publication Date:
October 15, 1993
Filing Date:
March 17, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L27/12; H01L21/02; H01L21/336; H01L29/78; H01L29/786; (IPC1-7): H01L29/784; H01L27/12
Attorney, Agent or Firm:
Kitano Yoshito