MANUFACTURE OF SEMICONDUCTOR DEVICE

Title:

MANUFACTURE OF SEMICONDUCTOR DEVICE

Document Type and Number:

Japanese Patent JPH11330381

Kind Code:

A

Abstract:

To provide a manufacture of a semiconductor device that can prevent alignment failures during the semiconductor manufacturing process and has a favorable yield.

When forming an element separation layer 4, a planarized TEOS film 34a in a trench 32 is removed shallower than the depth of a trench 32 to form a step in the trench 32. This step forms a step on a polysilicon layer 36, which is used as an alignment mark to align a mask during photolithography so that the polysilicon layer 36 is patterned to form a gate electrode 6. Thus, the gate electrode 6 can be formed without any alignment shift. Since only the top thin part of the insulating layer is removed, the step can be made small so that focus shift can be eliminated during photolithography.

Inventors:

KAWAI HIDETOSHI

Application Number:

JP13069798A

Publication Date:

November 30, 1999

Filing Date:

May 13, 1998

Export Citation:

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Assignee:

DENSO CORP

International Classes:

H01L21/76; H01L21/027; H01L27/08; H01L29/78; (IPC1-7): H01L27/08; H01L21/027; H01L21/76; H01L29/78

Attorney, Agent or Firm:

Yoji Ito (1 person outside)

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