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Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS59119767
Kind Code:
A
Abstract:

PURPOSE: To easily provide a good ohmic contact and a P-N junction and thus to obtain an FET of a III-V group compound semiconductor by a method wherein V-group semiconductor layers of different thicknesses are formed on a III- Vgroup compound semiconductor substrate, and one of them is fused by the irradiation with energy rays.

CONSTITUTION: An N-layer 2 approx. 0.2μm thick is formed on the semiinsulation GaAs substrate 1 by doping Si, and Ge layers 3 and 4 approx. 30nm and 60nm thick are selectively provided. When the intensity is selected by the irradiation with laser light L from the back surface, the thin film 3 has a large transmittance and does not increase to the melting point of Ge, and only the thick layers 4 and the neighborhood of the layer 2 contacting the layers are fused. Therefore, N+ layers 5 of the alloy of Ga, As, and Ge can be formed. The ratio of Ge composition in the layer 5 decreases as it goes toward the bottom. The layer 3 does not fuse and forms the P-N junction in the neighborhood of the interface between the substrate 1. Next, a gate, a source, and a drain electrode 6 and 7 are attached by means of the same material of Al, thus completing the III-V group compound semiconductor FET of a high speed and a low consumed power.


Inventors:
NANBU KAZUO
SATOU TAKASHI
YAMAGUCHI YASUHIRO
Application Number:
JP23261582A
Publication Date:
July 11, 1984
Filing Date:
December 25, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/808; H01L21/265; H01L21/268; H01L21/28; H01L21/337; H01L29/80; (IPC1-7): H01L21/265; H01L21/28
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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