PURPOSE: To enhance the flexibility of wiring design and improve the integration degree by a method wherein the polycrystalline Si wiring layer of the first layer is simultaneously formed when a polycrystalline Si gate electrode layer constituting an MOS transistor is formed, the surface layer part of the wiring layer being changed into an SiO2 by heat treatment, and the wiring layer of the second layer then being provided thereon.

CONSTITUTION: A thick field SiO2 film 2 is formed in the periphery of a P type Si substrate 1 with a P+ type region 3 for preventing the generation of a parastic MOS underlying the film the N+ type source 4 and drain 5 regions are diffusion-formed in the substrate 1 therebetween. Next, the gate electrode 7 made of polycrystalline Si is formed between these regions, and at the same time the wiring layers 9 and 10 of the first layer of polycrystalline Si are formed via thin SiO2 film 11. Thereafter, heat treatment is carried out, and the electrode 7 is surrounded with a gate insulation film made of an SiO2 film 6 generated. At the same time, the surface layer parts of the wirings layers 9 and 10 are changed into the SiO2 film 12 serving as the interlayer insulation film. Thus, the film 2 with no pin holes is obtained, and the wiring layer 13 of the second layer is connected to the film via aperture.