Title:
MANUFACTURE OF THIN FILM TRANSISTOR
Document Type and Number:
Japanese Patent JP3161466
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To form contact holes of source and drain regions and of gate elec trode in the uniform shape and size in the substrate through reduction of wiring resistance of gate line and capacitive line, by conducting the etching in the two steps to the first and second silicon dioxide layers in different etching rates.
SOLUTION: A first contact hole 107 to lead the lead wiring from the impurity-doped and actively annealed source/drain areas 101 is opened to a first silicon dioxide layer 103. A metal material which does not react with polycrystalline silicon at the temperature of 200°C or lower is formed only on a gate electrode 105a and a capacitive line 106 to lower the wiring resistance of the gate line and capacitive line. In view of improving film quality after deposition of a second silicon dioxide layer 108, annealing is executed at a temperature where polycrystalline silicon of the capacitive lines of the gate electrodes 105, 106 and a metal material are not converted into silicides. a second contact hole 109 is opened to the second silicon dioxide layer 108 to obtain the lead wiring from the source/drain region 101 and gate electrode 104.
Inventors:
Takashi Inoue
Application Number:
JP2000087268A
Publication Date:
April 25, 2001
Filing Date:
February 20, 1991
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G02F1/1368; G02F1/136; H01L21/28; H01L21/3205; H01L21/336; H01L21/768; H01L23/52; H01L29/786; (IPC1-7): H01L29/786; G02F1/1368; H01L21/3205
Domestic Patent References:
| JP242419A | ||||
| JP2285678A | ||||
| JP2245739A | ||||
| JP1227129A | ||||
| JP264615A | ||||
| JP62252171A |
Attorney, Agent or Firm:
Kisaburo Suzuki (2 outside)
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