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Title:
MANUFACTURING METHOD OF CIRCUIT AND MANUFACTURING DEVICE OF CIRCUIT, ANNEALING CONTROL METHOD AND ANNEALING CONTROL DEVICE AND INFORMATION STORAGE MEDIUM
Document Type and Number:
Japanese Patent JP2001297996
Kind Code:
A
Abstract:

To prevent useless diffusion of impurities in a silicon wafer as well while a stress in the silicon wafer is relaxed when the impurity-doped silicon wafer is subjected to spike annealing by an RTA method.

A silicon wafer heated up to an annealing temperature is cooled down at a high speed at first and is cooled down finally at a low speed. As the cooling-down speed is low from the middle of cooling-down, a stress in the wafer is relaxed and as the cooling-down is high until the middle of cooling- down, heat energy enough to cut the bonding of impurities of its reduced solubility to the wafer does not work on the impurities and impurities are not uselessly diffused in the wafer as the bonding of the impurities to the wafer is not cut.


Inventors:
MATSUDA TOMOKO
Application Number:
JP2000112335A
Publication Date:
October 26, 2001
Filing Date:
April 13, 2000
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L29/78; H01L21/265; H01L21/268; H01L21/324; H01L21/336; (IPC1-7): H01L21/265; H01L29/78
Domestic Patent References:
JPS60193343A1985-10-01
JPH02268422A1990-11-02
JPH0774180A1995-03-17
JPH10256538A1998-09-25
JPH1174210A1999-03-16
JPH11214323A1999-08-06
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)